1. Field of the Invention
This invention relates generally to the fabrication of semiconductor integrated circuit devices. In particular my invention is concerned with forming adjacent impurity regions within semiconductor substrates.
2. Description of the Prior Art
The formation of the various impurity regions required to fabricate integrated circuit transistors, diodes, resistors, etc., in a semiconductor chip requires very accurate positioning. It is necessary to very accurately control the alignment of the successive lithographic masks that are used for forming the impurity regions. Complex structures, such as bipolar and advanced FET integrated circuit devices, require a large number of masking steps; and successive masking operations depend to a large extent on the accuracy of the previous masking steps.
The allotted spacing between the apertures in lithographic masks must allow for mask misalignment, incorrect aperture size, overetching, etc. Said spacing becomes quite critical as the number of masks increases. However, these tolerance allowances waste space so as to reduce the packing density of the circuit elements on the substrate.
Typically, distinct impurity regions which are aligned with respect to each other are formed within the substrate by first forming a diffusion mask, such as silicon dioxide, atop the substrate. A resist mask is then applied, exposed and developed lithographically to define a first impurity region pattern. Windows are then etched in the silicon dioxide through the openings in the photoresist down to the substrate; the first impurity regions are then formed in the substrate by introducing impurities through the silicon dioxide windows. To form the other impurity regions, the substrate is typically reoxidized and a second photoresist mask is patterned lithographically to define the openings for the other impurity regions. Windows in the regrown oxide are then etched through the openings in the second photoresist pattern down to the substrate and impurities are introduced therethrough to form the other impurity regions.
This type of technique requires an accurately aligned lithographic mask for each step which involves the introduction of a distinct impurity, whether by diffusion or ion implantation. It is costly in terms of both direct expense for masks as well as reducing the overall yield of usable integrated circuit devices. Any substantial misalignment of the second mask with respect to the first ordinarily results in a defective wafer, which contains hundreds of individual chips.
Other, more recent techniques for forming distinct, aligned impurity regions involve the use of diffusion masks which are selectively etchable with respect to each other. For example, silicon dioxide and silicon nitride are attacked by buffered HF and hot phosphoric acid, respectively, whereas the former acid does not substantially affect silicon nitride and the latter acid does not substantially affect silicon dioxide.
Typically, the nitride is first deposited atop the oxide on the substrate. A single resist mask and conventional lithographic techniques are then used to form in a single step a pattern of openings in the nitride which define both sets of distinct impurity regions. Next, another photoresist mask, which is non-critical in terms of alignment and is commonly termed a "blocking" mask, is applied, exposed and developed to expose only those portions of the silicon dioxide layer which are atop the first set of impurity regions to be formed. The silicon dioxide layer is selectively etched in buffered HF, with the silicon nitride layer itself acting as a mask. The first impurity regions are then introduced into the substrate through the windows in the silicon dioxide layer. A second photoresist masking step is then used to form the second set of impurity regions in substantially the same manner.
This improved process and variations of it, while not requiring critically aligned resist masks, still require the use of separate lithographic masking steps for the formation of each distinct set of regions.
Another technique which has been suggested for forming distinct, aligned impurity regions involves the use of differential thicknesses of the diffusion masking layer, typically silicon dioxide. Such a technique is described for example, in the article by C. H. Lee entitled "Self-Aligning Subcollector and Isolation Regions in a Semiconductor Transistor", IBM Technical Disclosure Bulletin, Volume 20, No. 6, November 1977, pages 2233-34. This technique is similar to the above-described use of selectively etchable diffusion layers in that separate photolithographic masks are required, although they need not be aligned with extreme accuracy.
The previous techniques have been applied to the formation of various types of impurity regions, including those cases where two highly-doped regions are required to be adjacent each other, e.g., the subcollector and isolation regions of a bipolar transistor. It is necessary that such regions not overlap unduly lest dislocations occur within the regions. These problems can be avoided by designing the masking operation to allow for greater distances between the regions, thereby reduces circuit density. Alternatively, the dislocations may be accepted as part of the overall product design; this results in reduced quantities of usable chips based upon the statistical distribution of dislocations and their effect on product performance.